950ps max. data to output extended 100e v ee range of ?.2v to ?.5v 850ps max. latch enable to output separate select controls differential outputs fully compatible with industry standard 10kh, 100k ecl levels internal 75k ? input pulldown resistors fully compatible with motorola mc10e/100e256 available in 28-pin plcc package features 3-bit 4:1 mux-latch the sy10/100e256 offer three 4:1 multiplexers followed by latches with differential outputs designed for use in new, high-performance ecl systems. separate select controls are provided for the leading 2:1 mux pairs (see block diagram). when the latch enable (len) is at a logic low, the latch is transparent and output data is controlled by the multiplexer select controls. a logic high on len latches the outputs. the master reset (mr) overrides all other controls to set the q outputs low. description sy10e256 sy100e256 final rev.: c amendment: /1 issue date: february, 1998 block diagram pin configuration pin function d 0x ? 2x parallel data inputs sel 1a , sel 1b first-stage select inputs sel 2 second-stage select input len latch enable mr master reset q 0 , q 0 ? 2 , q 2 data outputs v cco v cc to output pin names top view plcc j28-1 26 27 28 1 2 3 4 18 17 16 15 14 13 12 25 24 23 22 21 20 19 5 6 7 8 9 10 11 d 0b v cco q 0 d 0a d 1d d 0c d 0d v ee d 1c sel 2 mr len sel 1a sel 1b v cco d 2c d 2d d 1a d 1b d 2b d 2a v cc q 2 q 1 v cco q 2 q 1 q 0 d r e n q 0 q 0 q 1 q 1 q 2 q 2 d r e n d r e n d 0a sel 1b d 0b d 0c d 0d d 1a d 1b d 1c d 1d d 2a d 2b d 2c d 2d sel 1a sel 2 len mr 1
2 sy10e256 sy100e256 micrel pin state operation sel 2 h output c/d data sel 1a h input d data sel 1b h input b data truth table ac electrical characteristics v ee = v ee (min.) to v ee (max.); v cc = v cco = gnd t a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition t plh propagation delay to output ps t phl d 400 600 900 400 600 900 400 600 900 sel 1 550 775 1050 550 775 1050 550 775 1050 sel 2 450 650 900 450 650 900 450 650 900 len 350 500 800 350 500 800 350 500 800 mr 350 600 825 350 600 825 350 600 825 t s set-up time ps d 400 275 400 275 400 275 sel 1 600 300 600 300 600 300 sel 2 500 250 500 250 500 250 t h hold time ps d 300 275 300 275 300 275 sel 1 100 300 100 300 100 300 sel 2 200 250 200 250 100 250 t rr reset recovery time 700 600 700 600 700 600 ps t pw minimum pulse width, mr 400 400 400 ps t skew within-device skew 50 50 50 ps 1 t r rise/fall time 275 475 700 275 475 700 275 475 700 ps t f 20% to 80% dc electrical characteristics v ee = v ee (min.) to v ee (max.); v cc = v cco = gnd t a = 0 ct a = +25 ct a = +85 c symbol parameter min. typ. max. min. typ. max. min. typ. max. unit condition i ih input high current 150 150 150 a i ee power supply current ma 10e 69 83 69 83 69 83 100e 69 83 69 83 79 96 product ordering code ordering package operating code type range sy10e256jc j28-1 commercial sy10e256jctr j28-1 commercial sy100e256jc j28-1 commercial sy100e256jctr j28-1 commercial note: 1. within-device skew is defined as identical transitions on similar paths through a device.
3 sy10e256 sy100e256 micrel 28 lead plcc (j28-1) rev. 03
4 sy10e256 sy100e256 micrel micrel-synergy 3250 scott boulevard santa clara ca 95054 usa tel + 1 (408) 980-9191 fax + 1 (408) 914-7878 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel inc. ? 2000 micrel incorporated
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